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preliminary product information this document contains information for a new product. cirrus logic reserves the right to modify this product without notice. 1 copyright ? cirrus logic, inc. 2004 (all rights reserved) www.cirrus.com cs5341 105 db, 192 khz, multi-bit audio a/d converter features advanced multi-bit delta-sigma architecture 24-bit conversion supports all audio sample rates including 192 khz. 105 db dynamic range at 5 v -98 db thd+n high-pass filter to remove dc offsets analog/digital core supplies from 3.3 v to 5v supports logic levels between 1.8 v and 5 v. low-latency digital filter auto-mode selection general description the cs5341 is a complete analog-to-digital converter for digital audio systems. it performs sampling, analog-to- digital conversion, and anti-alias filtering, generating 24-bit values for both left and right inputs in serial form at sample rates up to 200 khz per channel. the cs5341 uses a 5th-order, multi-bit delta-sigma modulator followed by digital filtering and decimation, which removes the need for an external anti-alias filter. the cs5341 is ideal for audi o systems requiring wide dy- namic range, negligible distortion and low noise, such as set-top boxes, dvd-karaoke players, dvd recorders, a/v receivers, and automotive applications. ordering information cs5341-czz, lead free -10 to 70 c 16-pin tssop cs5341-dzz, lead free -40 to 85 c 16-pin tssop CDB5341 evaluation board voltage reference serial output interface digital filter high pass filter high pass filter decimation digital filter decimation dac - + s/h dac - + s/h ainr sclk sdout mclk rst vq lrck ainl filt+ m0 refgnd v l q lp filter q lp filter m1 vd gnd va 3.3v - 5.0v 3.3v - 5.0v 1.8v - 5.0v aug ?04 ds564pp2
cs5341 2 ds564pp2 table of contents 1 characteristics and specifications ......................................................................... 4 specified operating conditions ................................................................................. 4 absolute maximum ratings ........................................................................................... 4 analog characteristic-s (cs5341-cz/czz) ................................................................ 5 analog characteristics (cs5341-dzz) ....................................................................... 7 digital filter characteristics (cs5341-cz/czz/dzz) ............................................. 9 dc electrical characteristics................................................................................. 12 digital characteristics ............................................................................................... 12 thermal characteristics............................................................................................ 12 switching characteristics - serial audio port ................................................. 13 2 pin description ........................................................................................................... ...... 15 3 typical connection diagram ....................................................................................... 16 4 applications ............................................................................................................... ........ 17 4.1 single, double, and quad speed modes ......................................................................... 17 4.2 operation as either a clock master or slave ................................................................... 17 4.2.1 operation as a clock master ............................................................................... 18 4.2.2 operation as a clock slave ................................................................................. 18 4.2.3 master clock ....................................................................................................... 19 4.3 serial audio interface .................................................................................................... ... 19 4.4 power-up sequence ........................................................................................................ 2 0 4.5 analog connections ........................................................................................................ .20 4.6 grounding and power supply decoupling ....................................................................... 20 4.7 synchronization of multiple devices ................................................................................ 21 4.8 capacitor size on the reference pin (filt+) .................................................................. 21 5 parameter definitions ................................................................................................... 22 6 package dimensions ....................................... ................................................................ 2 3 7. revision history .......................................................................................................... .... 24 contacting cirrus logic support for all product questions and inquiries contact a cirrus logic sales representative. to find one nearest you go to www.cirrus.com/ important notice ?preliminary? product information describes products that are in production, but for which full characterization data is not ye t available. cirrus logic, inc. and its subsidiaries ("cirrus") believe that the information contained in this document is accurate and reliable. however, the informat ion is subject to change without notice and is provided "as is" without warranty of any kind (express or implied). customers are advised to obtain the latest version o f relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and condit ions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. no responsibili ty is assumed by cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of p atents or other rights of third parties. this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or implied under any p atents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. cirrus owns the copyrights associated with the information con tained herein and gives consent for copies to be made of the information only for use within your organization with respect to cirrus integrated circuits or other products of cirrus. this consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. certain applications using semiconductor products may involve potential risks of death, personal injury, or severe prop- erty or environmental damage (critical applications?). cirrus products are not designed, authorized or warranted for use in aircraft systems, military applications, products surgically implanted into the body, life support products or oth- er critical applications (including medical devices, aircraft systems or components and personal or automotive safety or security devices). inclusion of cirrus products in such applications is understood to be fully at the customers risk and cirrus disclaims and makes no warranty, express, statutory or implied, including the implied warranties of merchantabil- ity and fitness for particular purpose, with regard to any cirrus product that is used in such a manner. if the customer or customers customer uses or permits the use of cirrus products in critical applications, customer agrees, by such use, to fully indemnify cirrus, its officers, directors, employees, distributors and other agents from any and all liability, in- cluding attorneys fees and costs, that may result from or arise in connection with these uses. cirrus logic, cirrus, and the cirrus logic logo designs are trademarks of cirrus logic, inc. all other brand and product names in this document may be trademarks or service marks of their respective owners.
cs5341 ds564pp2 3 list of figures figure 1. single speed mode stopband rejection ....................................................................... 10 figure 2. single speed mode stopband rejection ....................................................................... 10 figure 3. single speed mode transition band (detail)................................................................. 10 figure 4. single speed mode passband ripple ........................................................................... 10 figure 5. double speed mode stopband rejection...................................................................... 10 figure 6. double speed mode stopband rejection...................................................................... 10 figure 7. double speed mode transition band (detail) ............................................................... 11 figure 8. double speed mode passband ripple .......................................................................... 11 figure 9. quad speed mode stopband rejection ........................................................................ 11 figure 10. quad speed mode stopband rejection ...................................................................... 11 figure 11. quad speed mode transition band (detail) ................................................................ 11 figure 12. quad speed mode passband ripple........................................................................... 11 figure 13. master mode, left justified sai ................................................................................... 14 figure 14. slave mode, left justified sai ..................................................................................... 1 4 figure 15. master mode, i 2 s sai .................................................................................................. 14 figure 16. slave mode, i 2 s sai .................................................................................................... 14 figure 17. typical connection diagram........................................................................................ 16 figure 18. cs5341 master mode clocking ................................................................................... 18 figure 19. left-justified serial audio interface ............................................................................. 19 figure 20. i 2 s serial audio interface............................................................................................. 19 figure 21. cs5341 recommended analog input buffer............................................................... 20 figure 22. cs5341 thd+n versus frequency ............................................................................. 21 list of tables table 1. speed modes and the associated output sample rates (fs)........................................ 17 table 2. cs5341 mode control................................................................................................... .. 17 table 3. master clock (mclk) ratios........................................................................................... 1 9 table 4. master clock (mclk) frequencies for standard audio sample rates .......................... 19 table 5. revision history ...................................................................................................... ........ 24
cs5341 4 ds564pp2 1 characteristics and specifications (all min/max characteristics and specifications are guaranteed over the specified operating conditions. typical performance characteristics and specifications are derived from measurements taken at typical supply voltages and t a = 25 c.) specified operating conditions (gnd = 0 v, all voltages with respect to 0 v.) notes: 1. this part is specified at typical analog voltages of 3.3 v and 5.0 v. see analog characteristics (cs5341- cz/czz) and analog characteristics (cs5341-dzz), below, for details. absolute maximum ratings (gnd = 0 v, all voltages with respect to ground.) (note 4) notes: 2. any pin except supplies. transient currents of up to 100 ma on the analog input pins will not cause src latch-up. 3. the maximum over/under voltage is limited by the input current. 4. operation beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. parameter symbol min typ max unit power supplies analog digital logic va vd vl 3.1 3.1 1.7 (note 1) 3.3 3.3 5.25 5.25 5.25 v v v ambient operating temperature commercial (-cz/-czz) (-dzz) t ac t ac -10 -40 - - 70 85 c c parameter symbol min max units dc power supplies: analog logic digital va vl vd -0.3 -0.3 -0.3 +6.0 +6.0 +6.0 v v v input current (note 2) i in - 10 ma analog input voltage (note 3) v in gnd-0.7 va+0.7 v digital input voltage (note 3) v ind -0.7 vl+0.7 v ambient operating temperature (power applied) t a -50 +95 c storage temperature t stg -65 +150 c
cs5341 ds564pp2 5 analog characteristics (cs5341-cz/czz) test conditions (unless otherwise speci- fied): input test signal is a 1 khz sine wave; measurement bandwidth is 10 hz to 20 khz. parameter symbol min typ max unit va = 3.3 v single speed mode fs = 48 khz dynamic range a-weighted unweighted 96 93 102 99 - - db db total harmonic distortion + noise (note 5) -1 db -20 db -60 db thd+n - - - -95 -79 -39 -89 - - db db db double speed mode fs = 96 khz dynamic range a-weighted unweighted 40 khz bandwidth unweighted 96 93 - 102 99 96 - - - db db db total harmonic distortion + noise (note 5) -1 db -20 db -60 db 40 khz bandwidth -1 db thd+n - - - - -95 -79 -39 -87 -89 - - - db db db db quad speed mode fs = 192 khz dynamic range a-weighted unweighted 40 khz bandwidth unweighted 96 93 - 102 99 96 - - - db db db total harmonic distortion + noise (note 5) -1 db -20 db -60 db 40 khz bandwidth -1 db thd+n - - - - -95 -79 -39 -87 -89 - - - db db db db va = 5.0 v single speed mode fs = 48 khz dynamic range a-weighted unweighted 99 96 105 102 - - db db total harmonic distortion + noise (note 5) -1 db -20 db -60 db thd+n - - - -98 -82 -42 -92 - - db db db double speed mode fs = 96 khz dynamic range a-weighted unweighted 40 khz bandwidth unweighted 99 96 - 105 102 99 - - - db db db total harmonic distortion + noise (note 5) -1 db -20 db -60 db 40 khz bandwidth -1 db thd+n - - - - -98 -82 -42 -95 -92 - - - db db db db
cs5341 6 ds564pp2 note: 5. referred to the typical full-scale input voltage quad speed mode fs = 192 khz dynamic range a-weighted unweighted 40 khz bandwidth unweighted 99 96 - 105 102 99 - - - db db db total harmonic distortion + noise (note 5) -1 db -20 db -60 db 40 khz bandwidth -1 db thd+n - - - - -98 -82 -42 -95 -92 - - - db db db db dynamic performance for all modes interchannel isolation - 90 - db dc accuracy interchannel gain mismatch - 0.1 - db gain error - 5 % gain drift - 100 - ppm/c analog input characteristics full-scale input voltage 0.53*va 0.56*va 0.59*va vpp input impedance - 25 - k ?
cs5341 ds564pp2 7 analog characteristics (cs5341-dzz) test conditions (unless otherwise specified): input test signal is a 1 khz sine wave; measurement bandwidth is 10 hz to 20 khz. parameter symbol min typ max unit va = 3.3 v single speed mode fs = 48 khz dynamic range a-weighted unweighted 94 91 102 99 - - db db total harmonic distortion + noise (note 6) -1 db -20 db -60 db thd+n - - - -95 -79 -39 -87 - - db db db double speed mode fs = 96 khz dynamic range a-weighted unweighted 40 khz bandwidth unweighted 94 91 - 102 99 96 - - - db db db total harmonic distortion + noise (note 6) -1 db -20 db -60 db 40 khz bandwidth -1 db thd+n - - - - -95 -79 -39 -87 -87 - - - db db db db quad speed mode fs = 192 khz dynamic range a-weighted unweighted 40 khz bandwidth unweighted 94 91 - 102 99 96 - - - db db db total harmonic distortion + noise (note 6) -1 db -20 db -60 db 40 khz bandwidth -1 db thd+n - - - - -95 -79 -39 -87 -87 - - - db db db db va = 5.0 v single speed mode fs = 48 khz dynamic range a-weighted unweighted 97 94 105 102 - - db db total harmonic distortion + noise (note 6) -1 db -20 db -60 db thd+n - - - -98 -82 -42 -90 - - db db db double speed mode fs = 96 khz dynamic range a-weighted unweighted 40 khz bandwidth unweighted 97 94 - 105 102 99 - - - db db db total harmonic distortion + noise (note 6) -1 db -20 db -60 db 40 khz bandwidth -1 db thd+n - - - - -98 -82 -42 -95 -90 - - - db db db db
cs5341 8 ds564pp2 note: 6. referred to the typical full-scale input voltage quad speed mode fs = 192 khz dynamic range a-weighted unweighted 40 khz bandwidth unweighted 97 94 - 105 102 99 - - - db db db total harmonic distortion + noise (note 6) -1 db -20 db -60 db 40 khz bandwidth -1 db thd+n - - - - -98 -82 -42 -95 -90 - - - db db db db dynamic performance for all modes interchannel isolation - 90 - db dc accuracy interchannel gain mismatch - 0.1 - db gain error - 10 % gain drift - 100 - ppm/c analog input characteristics full-scale input voltage 0.5*va 0.56*va 0.62*va vpp input impedance - 25 - k ?
cs5341 ds564pp2 9 digital filter characteristics (cs5341-cz/czz/dzz) note: 7. response shown is for fs equal to 48 khz. filter characteristics scale with fs. parameter symbol min typ max unit single speed mode fs = 48 khz passband (-0.1 db) 0 - 23.5 khz passband ripple - - 0.035 db stopband 27.3 - - khz stopband attenuation 70 - - db total group delay (fs = output sample rate) t gd - 12/fs - s double speed mode fs = 96 khz passband (-0.1 db) 0 - 47 khz passband ripple - - 0.025 db stopband 53.8 - - khz stopband attenuation 69 - - db total group delay (fs = output sample rate) t gd -9/fs - s quad speed mode fs = 192 khz passband (-0.1 db) 0 - 50 khz passband ripple - - 0.025 db stopband 96 - - khz stopband attenuation 60 - - db total group delay (fs = output sample rate) t gd -5/fs - s high pass filter characteristics frequency response -3.0 db -0.13 db (note 7) -1 20 - - hz hz phase deviation @ 20 hz (note 7) - 10 - deg passband ripple - - 0 db
cs5341 10 ds564pp2 figure 1. single speed mode stopband rejection figure 2. single speed mode stopband rejection figure 3. single speed mode transition band (detail) figure 4. single speed mode passband ripple figure 5. double speed mode stopband rejection figure 6. double speed mode stopband rejection -140 -130 -120 - 110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0 .0 0 .1 0 .2 0 .3 0.4 0.5 0.6 0 .7 0 .8 0 .9 1.0 frequency (normalized to fs) amplitude (db) -140 -130 -120 - 110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60 frequency (normalized to fs) amplitude (db) -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55 frequency (norm alized to fs) amplitude (db) -0.10 -0.08 -0.06 -0.04 -0.02 0.00 0.02 0.04 0.06 0.08 0.10 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 frequency (norm alized to fs) amplitude (db) -140 -130 -120 - 110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0 .0 0 .1 0 .2 0 .3 0.4 0.5 0.6 0 .7 0 .8 0 .9 1.0 frequency (normalized to fs) amplitude (db) -140 -130 -120 - 110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60 frequency (normalized to fs) amplitude (db)
cs5341 ds564pp2 11 figure 7. double speed mode transition band (detail) figure 8. double speed mode passband ripple figure 9. quad speed mode stopband rejection figure 10. quad speed mode stopband rejection figure 11. quad speed mode transition band (detail) figure 12. quad speed mode passband ripple -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0.46 0.47 0.48 0.49 0.50 0.51 0.52 frequency (norm alized to fs) amplitude (db) -0.10 -0.08 -0.06 -0.04 -0.02 0.00 0.02 0.04 0.06 0.08 0.10 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 frequency (norm alized to fs) amplitude (db) -140 -130 -120 - 110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0 .0 0 .1 0 .2 0 .3 0.4 0.5 0.6 0 .7 0 .8 0 .9 1.0 frequency (normalized to fs) amplitude (db) -140 -130 -120 - 110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 frequency (normalized to fs) amplitude (db) -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 frequency (norm alized to fs) amplitude (db) -0.10 -0.08 -0.06 -0.04 -0.02 0.00 0.02 0.04 0.06 0.08 0.10 0.00 0.03 0.05 0.08 0.10 0.13 0.15 0.18 0.20 0.23 0.25 0.28 frequency (normalized to fs) amplitude (db)
cs5341 12 ds564pp2 dc electrical characteristics (gnd = 0 v, all voltages with respect to 0 v. mclk=12.288 mhz; master mode) notes: 8. power down mode is defined as rst = low with all clocks and data lines held static. 9. valid with the recommended capacitor values on filt+ and vq as shown in the typical connection diagram. digital characteristics thermal characteristics parameter symbol min typ max unit dc power supplies: positive analog positive digital positive logic va vd vl 3.1 3.1 1.7 - - - 5.25 5.25 5.25 v v v power supply current va = 5 v (normal operation) va = 3.3 v vl,vd = 5 v vl,vd = 3.3 v i a i a i d i d - - - - 21 18.2 15 9 23.1 20 16.5 10 ma ma ma ma power supply current va = 5 v (power-down mode) (note 8) vl,vd=5 v i a i d - - 1.5 0.4 - - ma ma power consumption vl, vd, va = 5 v (normal operation) vl, vd, va = 3.3 v (power-down mode) - - - - - - 180 90 9.5 198 100 - mw mw mw power supply rejection ratio (1 khz) (note 9) psrr - 65 - db v q nominal voltage output impedance - - va 2 25 - - v k ? filt+ nominal voltage output impedance maximum allowable dc current source/sink - - - va 18 0.01 - - - v k ? ma parameter symbol min typ max units high-level input voltage (% of vl) v ih 70% - - v low-level input voltage (% of vl) v il --30%v high-level output voltage at i o = 100 a(% of vl) v oh 70% - - v low-level output voltage at i o =100 a(% of vl) v ol --15%v input leakage current i in -- 10 a parameter symbol min typ max unit allowable junction temperature - - 135 c junction to ambient thermal impedance ja -75 - c/w ambient operating temperature (-cz/-czz) (power applied) (-dzz) t a t a -10 -40 - - +70 +85 c c
cs5341 ds564pp2 13 switching characteristics - serial audio port (logic "0" = gnd = 0 v; logic "1" = vl, c l = 20 pf) * for a description of speed modes, please refer to table 1 on page 17. parameter symbol min typ max unit mclk specifications mclk period t clkw 36 - 45 ns 72 - 1953 ns mclk pulse width high t clkh 15 - - ns mclk pulse width low t clkl 15 - - ns master mode sclk falling to lrck t mslr -20 - 20 ns sclk falling to sdout valid t sdo 0-32ns sclk duty cycle - 50 - % slave mode single speed* lrck duty cycle 40 50 60 % sclk period t sclkw 156 - - ns sclk low t sclkhl 55 - - ns sclk falling to sdout valid t dss --32ns sclk falling to lrck edge t slrd -20 - 20 ns double speed* lrck duty cycle 40 50 60 % sclk period t sclkw 156 - - ns sclk low t sclkhl 55 - - ns sclk falling to sdout valid t dss --32ns sclk falling to lrck edge t slrd -20 - 20 ns quad speed* lrck duty cycle 40 50 60 % sclk period t sclkw 78 - - ns sclk low t sclkhl 40 - - ns sclk falling to sdout valid t dss --32ns sclk falling to lrck edge t slrd -8 - 8 ns
cs5341 14 ds564pp2 sclk output t mslr sdout t sdo lrck output msb msb-1 sclk input lrck input sclkl t dss t msb msb-1 msb-2 lrdss t sclkh t t sclkw sdout srd l t figure 13. master mode, left justified sai figure 14. slave mode, left justified sai sclk output t mslr t sdo lrck output msb sdout sclk input lrck input sclkl t dss t msb msb-1 sclkh t t sclkw sdout figure 15. master mode, i 2 s sai figure 16. slave mode, i 2 s sai
cs5341 ds564pp2 15 2 pin description pin name # pin description m0 m1 1 16 mode selection ( input ) - determines the operational mode of the device. mclk 2 master clock ( input ) - clock source for the delta-sigma modulator and digital filters. vl 3 logic power ( input ) - positive power for the digital input/output. sdout 4 serial audio data output ( output ) - output for two?s complement serial audio data. gnd 5,14 ground ( input ) - ground reference. must be connected to analog ground. vd 6 digital power ( input ) - positive power supply for the digital section. sclk 7 serial clock ( input / output ) - serial clock for the serial audio interface. lrck 8 left right clock ( input / output ) - determines which channel, left or right, is currently active on the serial audio data line. rst 9 reset ( input ) - the device enters a low power mode when low. ainl ainr 10 12 analog input ( input ) - the full scale analog input level is specified in the analog charac- teristics specification table. vq 11 quiescent voltage (output) - filter connection for the internal quiescent reference voltage. va 13 analog power ( input ) - positive power supply for the analog section. filt+ 15 positive voltage reference ( output ) - positive reference voltage for the internal sampling circuits. m0 m1 mclk filt+ vl ref_gnd sdout va gnd ainr vd vq sclk ainl lrck rst 1 2 3 4 5 6 7 8 5 1 2 6 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 5 1 2 6 16 15 14 13 12 11 10 9
cs5341 16 ds564pp2 3 typical connection diagram filt+ v 0.1 f a/d converter sclk cs5341 mclk vq 1 f + rst va l 1 f 1.8v to 5v 1 f + + sdout gnd lrck power down and mode settings audio data processor timing logic and clock 0.1 f 0.1 f 0.1 f refgnd 1 f + ainl ainr 3.3v to 5v 1 f + 0.1 f 3.3v to 5v ? 5.1 v d 0.1 f ? 10k vl or gnd * pull-up to vl for i 2 s pull-down to gnd for lj * m0 m1 analog input buffer figure 21 ** ** resistor may only be used if vd is derived from va. if used, do not drive any other logic from vd *** *** capacitor value affects low frequency distortion performance as described in section 4.8 figure 17. typical connection diagram
cs5341 ds564pp2 17 4 applications 4.1 single, double, and quad speed modes the cs5341 can support output sample rates from 2 khz to 200 khz. the proper speed mode can be determined by the desired output sample rate and the external mclk/lrck ratio, as shown in table 1. * quad speed mode, 64x only available in master mode. table 1. speed modes and the associated output sample rates (fs) 4.2 operation as either a clock master or slave the cs5341 supports operation as either a clock master or slave. as a clock master, the lrck and sclk pins are outputs with the left/right and serial clocks synchronously generated on-chip. as a clock slave, the lrck and sclk pins are inputs and require the left/right and serial clocks to be externally generated. the selection of clock master or slave is made via the mode pins as shown in table 2. speed mode mclk/lrck ratio output sample rate range (khz) single speed mode 512x 43 - 54 256x 2 - 54 double speed mode 256x 86 - 108 128x 50 - 108 quad speed mode 128x 172 - 200 64x* 100 - 200 m1 (pin 16) m0 (pin 1) mode 0 0 clock master, single speed mode 0 1 clock master, double speed mode 1 0 clock master, quad speed mode 1 1 clock slave, all speed modes table 2. cs5341 mode control
cs5341 18 ds564pp2 4.2.1 operation as a clock master as a clock master, lrck and sclk operate as outputs. the left/right and serial clocks are internally derived from the master clock with the left/right clock equal to fs and the serial clock equal to 64x fs, as shown in figure 18. 4.2.2 operation as a clock slave lrck and sclk operate as inputs in clock slave mode. it is recommended that the left/right clock be synchronously derived from the master clock and must be equal to fs. it is also recommended that the serial clock be synchronously derived from the master clock and be equal to 64x fs to maximize system performance. a unique feature of the cs5341 is the automatic selection of either single, double or quad speed mode when op- erating as a clock slave. the auto-mode select feature negates the need to configure the mode pins to correspond to the desired mode. the auto-mode selection feature supports all standard audio sample rates from 2 to 200 khz. however, there are ranges of non-standard audio sample rates that are not supported when operating with a fast mclk (512x, 256x, 128x for single, double, and quad speed modes respectively). please refer to table 1 for sup- ported sample rate ranges. 128 256 64 m0 m1 lrck output (equal to fs) single speed quad speed double speed 00 01 10 2 4 1 sclk output single speed quad speed double speed 00 01 10 2 1 0 1 mclk auto-select figure 18. cs5341 master mode clocking
cs5341 ds564pp2 19 4.2.3 master clock the cs5341 requires a master clock (mclk) which runs the internal sampling circuits and digital filters. there is also an internal mclk divider which is automatically activated based on the speed mode and frequency of the mclk. table 3 shows a listing of the external mclk/lrck ratios that are required. table 4 lists some common au- dio output sample rates and the required mclk frequency. please note that not all of the listed sample rates are supported when operating with a fast mclk (512x, 256x, 128x for single, double, and quad speed modes respec- tively). 4.3 serial audio interface the cs5341 supports both i 2 s and left justified serial audio formats. upon start-up, the cs5341 will detect the logic level on sdout (pin 4). a 10 k ? pull-up to vl is needed to select i 2 s format, and a 10 k ? pull-down to gnd is needed to select left justified format. please see figures 13 through 16 on page 14, for more information on the required timing for the two serial audio interface formats. single speed mode double speed mode quad speed mode mclk/lrck ratio 256x, 512x 128x, 256x 64x*,128x * quad speed, 64x only available in master mode. table 3. master clock (mclk) ratios sample rate (khz) mclk (mhz) 32 8.192 44.1 11.2896 22.5792 48 12.288 24.576 64 8.192 88.2 11.2896 22.5792 96 12.288 24.576 192 12.288 24.576 table 4. master clock (mclk) frequencies for standard audio sample rates sdata 23 22 7 6 23 22 sclk lrck 23 22 54 32 10 8 76 54 32 10 8 9 9 left channel right channel figure 19. left-justified serial audio interface sdata 23 22 8 7 23 22 sclk lrck 23 22 65 43 21 0 87 65 43 21 0 9 9 left channel right channel figure 20. i 2 s serial audio interface
cs5341 20 ds564pp2 4.4 power-up sequence reliable power-up can be accomplished by keeping the device in reset until the power supplies, clocks and config- uration pins are stable. it is also recommended that reset be enabled if the analog or digital supplies drop below the minimum specified operating voltages to prevent power glitch related issues. 4.5 analog connections the analog modulator samples the input at 6.144 mhz. the digital filter will reject signals within the stopband of the filter. however, there is no rejection for input signals which are multiples of the input sampling frequency (n 6.144 mhz), where n=0,1,2,... refer to figure 21 which shows the suggested filter that will attenuate any noise energy at 6.144 mhz, in addition to providing the optimum source impedance for the modulators. the use of capac- itors which have a large voltage coefficient (such as general purpose ceramics) must be avoided since these can degrade signal linearity. 4.6 grounding and power supply decoupling as with any high resolution converter, the cs5341 requires careful attention to power supply and grounding arrange- ments if its potential performance is to be realized. figure 17 shows the recommended power arrangements, with va and vl connected to clean supplies. vd, which powers the digital filter, may be run from the system logic supply or may be powered from the analog supply via a resistor. in this case, no additional devices should be powered from vd. decoupling capacitors should be as near to the adc as possible, with the low value ceramic capacitor being the nearest. all signals, especially clocks, should be kept away from the filt+ and vq pins in order to avoid un- wanted coupling into the modulators. the filt+ and vq decoupling capacitors, particularly the 0.01 f, must be positioned to minimize the electrical path from filt+ and ref_gnd. the CDB5341 evaluation board demonstrates the optimum layout and power supply arrangements. to minimize digital noise, connect the adc digital outputs only to cmos inputs. 100k ? + 634 ? 91 ? - 2200 pf 470 pf cog cs5341 ainl ainl cog 100k ? 4.7 uf va 100k ? ainr 100k ? 4.7 uf va 634 ? 91 ? + - 470 pf cog c s5341 ainr 2200 pf cog figure 21. cs5341 recommended analog input buffer
cs5341 ds564pp2 21 4.7 synchronization of multiple devices in systems where multiple adcs are required, care must be taken to achieve simultaneous sampling. to ensure synchronous sampling, the mclk and lrck must be the same for all of the cs5341?s in the system. if only one master clock source is needed, one solution is to place one cs5341 in master mode, and slave all of the other cs5341?s to the one master. if multiple master clock sources are needed, a possible solution would be to supply all clocks from the same external source and time the cs5341 reset with the inactive (falling) edge of mclk. this will ensure that all converters begin sampling on the same clock edge. 4.8 capacitor size on the reference pin (filt+) the cs5341 requires an external capacitance on the internal reference voltage pin, filt+. the size of this decou- pling capacitor will affect the low frequency distortion performance as shown in figure 22, with larger capacitor val- ues used to optimize low frequency distortion performance. figure 22. cs5341 thd+n versus frequency 47 uf 100 uf 22 uf 10 uf 6.8 uf 4.7 uf 3.3 uf 2.2 uf 1 uf 5.6 uf
cs5341 22 ds564pp2 5 parameter definitions dynamic range the ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. dynamic range is a signal-to-noise ratio measurement over the specified bandwidth made with a -60 dbfs signal. 60 db is added to resulting measurement to refer the measurement to full-scale. this technique ensures that the distortion components are below the noise level and do not affect the measurement. this measurement technique has been accepted by the audio engineering society, aes17-1991, and the electronic industries association of japan, eiaj cp-307. expressed in decibels. total harmonic distortion + noise the ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 hz to 20 khz), including distortion components. expressed in decibels. measured at -1 and -20 dbfs as suggested in aes17-1991 annex a. frequency response a measure of the amplitude response variation from 10 hz to 20 khz relative to the amplitude response at 1 khz. units in decibels. interchannel isolation a measure of crosstalk between the left and right channels. measured for each channel at the converter's output with no signal to the input under test and a full-scale signal applied to the other channel. units in decibels. interchannel gain mismatch the gain difference between left and right channels. units in decibels. gain error the deviation from the nominal full-scale analog input for a full-scale digital output. gain drift the change in gain value with temperature. units in ppm/c. offset error the deviation of the mid-scale transition (111...111 to 000...000) from the ideal. units in mv.
cs5341 ds564pp2 23 6 package dimensions notes: 1. ?d? and ?e1? are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. dimension ?b? does not include dambar protrusion/intrusion. allowable dambar protrusion shall be 0.13 mm total in excess of ?b? dimension at maximum material condition. dambar intrusion shall not reduce dimension ?b? by more than 0.07 mm at least material condition. 3. these dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips. inches millimeters note dim min nom max min nom max a -- -- 0.043 -- -- 1.10 a1 0.002 0.004 0.006 0.05 -- 0.15 a2 0.03346 0.0354 0.037 0.85 0.90 0.95 b 0.00748 0.0096 0.012 0.19 0.245 0.30 2,3 d 0.193 0.1969 0.201 4.90 5.00 5.10 1 e 0.248 0.2519 0.256 6.30 6.40 6.50 e1 0.169 0.1732 0.177 4.30 4.40 4.50 1 e -- 0.026 bsc -- -- 0.065 bsc -- l 0.020 0.024 0.028 0.50 0.60 0.70 0 4 8 0 4 8 jedec #: mo-153 controlling dimension is millimeters 16l tssop (4.4 mm body) package drawing e n 1 23 e b 2 a1 a2 a d seating plane e1 1 l side view end view top view
cs5341 24 ds564pp2 7. revision history release date changes a1 february 2003 -initial advance release. a2 july 2003 -modified serial port timing specs. -added applications section on speed mode detect. pp1 june 2004 -change 2700 pf capacitors to 2200 pf in analog input buffer diagram. -update output sample rate range on page 17. -add new applications section about capacitors on filt+ pin. -corrected max mclk period under ?switching characteristics? on page 13. -add cs5341-czz as an available part-number. -replace available part number cs5341-dz with cs5341-dzz. -initial preliminary product release. pp2 aug 2004 update data sheet to include lead-free option. table 5. revision history

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